How does SPW47N60C3 POWER MOSFET work?

could someone help me solve this problem?

I have to drive a Power mosfet SPW47N60C3 for 600V, 47 An and it has an input capacity of about 12 nF.

The recurrence exchange should be 200 kHz and with a short rise and fall time (about 50 ns). Everything is on the top driver's side and must be fast. I will use the appropriate optocoupler if it is as well for the pilot on the low side.

Would you be able to give me a correct sign for the driver?

To evaluate the exchange speed, Qgd emits more than Ciss. Qgd is frequently called the Miller door todeplete load since it is the input load required when the no-load voltage of the MOSFET oscillates from completely on to off (or back). This refers to figure 11 of the data sheet, and is shown as an average of 121nC, which is not terrible for a high voltage FET of 415W. Adept's adaptation of a similar piece includes "Low Miller Capacitance" on the first page of the fact sheet.

The load equation tells us that you will need I = Q/t = 121/50 = 2.4A door drive to switch this part in 50ns. I keep a combination of FET driver chips to process FETs of different sizes. For example, the TC4427 is a double conductor rated at 1.5A, the TC4424 is a double 3A and the TC4420 is a single conductor 6A. Yet I would suggest section 6A for your huge FET. I would use a small input resistance of 1.5 ohms and keep the FET conductors to the short door wires. Keep the path from the source to the driver's GND handle short and instantly parallel to the inductance of the door prompt limit. Similar jacks for the 0.1uF shot at by bypassing the IC driver.

I would start my tests at low voltage and without load. I would evaluate the input and source voltages by changing to check the nature of my FET-druve low inductance wiring. For example, I would run the high side FET with its opto-coupler, but without the 400V on its exhaustion, and without the low side switch. Indeed, I would ground the source of the FET (to maintain the gate and source voltages within the range for my degree) and I would use a short resistive load to HV. I would have the FET beat for short heartbeats (to avoid overheating the resistance) and deliberately measure the lead inductance peaks, which will increase as the heap current develops. Finally, I would use an inductive load to evaluate high current destruction peaks.